The present invention relates to a control circuit for a buffer for outputting data from a memory device, and particularly to an output buffer precharge control circuit for use in detecting an address transition in which the output node is shifted to a desired level before the valid data is outputted by arranging that, when a node is precharged to invalid data, the precharge path is divided according to whether the invalid data is ".0." or "1", and if the output data is "1", the output node is discharged, while, if the output data is ".0.", the output node is charged.
A semiconductor memory device writes external data into the internal memory cells, and, if required, reads out to output the stored data from the internal memory cells. A number of internal steps are performed in carrying out such readings and writings.
The procedure of outputting data consists of a plurality of steps;
supply of column address signal.fwdarw.input/output (I/O) gating responsive thereto and connecting a signal through a bit line to an input/output line.fwdarw.supplying a data enable signal selecting.fwdarw.a data bus.fwdarw.outputting data.
That is, if a column address signal is supplied, then a gating pulse for selecting an I/O terminal is emitted and then, an I/O line is selected. Then, at the steps of connecting a signal to the I/O line and supplying the data enable signal, a second data sensing is carried out to step up the small voltage of the I/O line to a higher voltage, to select a data bus, and to output a data signal.
A data signal conversion is required between the data bus and the data output such that the signal level which has been a CMOS level before the data bus has to become a TTL level in its output. Accordingly, an output buffer is used in order to shift the level of the signal.
A circuit as shown in FIGS. 1 and 2 has been used conventionally for the level shifting of the output buffer, but the precharge section 9 of FIG. 1 is kept in a turned-on or turned-off state together with MOS transistors M1, M2 owing to the function of a control precharge pulse DCPP, with the result that a DC current loss is caused, thereby making it impossible to maintain the precharge level at a high impedance state.
Meanwhile, in the circuit of FIG. 2, the DC current dissipation can be prevented through a gating by means of the control precharge pulse DCPP, but in the case where the invalid data has a level of "1", the DC current dissipation can not be avoided, and the use of a large size MOS transistor is required in the precharge section 9.